1. Field of the Invention
The present invention relates to a circuit for generating an internal address in a semiconductor memory device, and in particular to an improved circuit for generating an internal address in a semiconductor memory device which can reduce power consumption in a self-refresh operation, by generating an internal refresh address to refresh a partial array selected according to an external command.
2. Description of the Background Art
The general constitution of the DRAM will now be explained with reference to FIG. 1 to provide background information on the technical field to which the present invention pertains. Referring to FIG. 1, the DRAM includes: a memory cell array unit 10 for storing data; a row address buffer unit 11 for receiving an m bit row address; a column address buffer unit 12 for receiving an n bit column address; a row decoder unit 13 for selecting a word line(s) of the memory cell array unit 10 according to the output signal from the row address buffer unit 11; a column decoder unit 14 for selecting a bit line(s) of the memory cell array unit 10 according to the output signal from the column address buffer unit 12; a data input buffer unit 15 for receiving data; and a data output buffer unit 16 for outputting data. In addition, the DRAM further includes: a sense amp unit 17 connected to the bit line(s) of the memory cell array, for reading a data signal(s) from a selected cell(s), and amplifying the data signal(s); an I/O gate circuit unit 18 for selectively connecting the bit line(s) of the memory cell array to the data input and output buffers 15 and 16 in response to the output signal(s) from the column decoder unit 14; and a chip control unit 20 for controlling the operation of peripheral circuits of the memory cell array unit 10.
As is well-known, one memory cell of the DRAM includes one select transistor and one data storage capacitor. Accordingly, the DRAM has been widely used as a semiconductor memory device for increasing the integration density on a semiconductor substrate.
However, since electric charges leak through the storage capacitor or select transistor, the DRAM needs to periodically perform a refresh operation to recharge the DRAM cells. As illustrated in FIG. 1, the DRAM further includes a refresh circuit unit 30 for controlling the data signals stored in the memory cells to be periodically amplified by the sense amp unit 17 and re-written on the memory cells, differently from the SRAM and non-volatile semiconductor memory device. The refresh circuit unit 30 includes: a refresh timer unit 31 for generating timing signal(s) for periodically performing the refresh operation; a refresh control unit 32 for controlling the whole operation relating to the refresh operation of the memory device according to the timing signal(s); and a refresh address generating unit 33 controlled by the refresh control unit 32, for generating internal refresh addresses.
A few methods for refreshing the DRAM cells have been widely employed. The main refresh methods will now be explained in brief.
In a RAS only refresh (ROR), while a column address strobe bar /CAS signal maintains a precharge level, a row address strobe bar /RAS signal is enabled to refresh cells. In the ROR, refresh addresses must be externally inputted to the memory device to perform the respective refresh operations, and address buses connected to the memory device cannot be used for other purposes during the refresh operations.
A CAS-before-RAS refresh (CBR) generates a row address in the refresh timer unit 31 built in the DRAM chip to perform the refresh operation, instead of externally inputting the refresh address.
In another refresh method, a hidden refresh is known as a combination of a read operation and a CBR operation. When /CAS is enabled at a low level in a read cycle, the output data maintains an effective state. Here, when /RAS reaches a high level and then returns to a low level, the CBR state is maintained, and thus one cycle of the CBR refresh is finished. The data output buffer unit 16 is controlled merely by /CAS, and thus the effective data are outputted in the whole cycle. Accordingly, it looks like a normal read operation. However, the refresh operation is executed by using an internal address generated by a CBR counter. That is why it is called a hidden refresh.
As described above, the ROR refresh, the CBR refresh and the hidden refresh are pulse refresh methods wherein a /RAS signal is externally inputted, and the refresh address is externally inputted or internally generated according to a control clock state. Recently, a /RAS signal which is a refresh synchronous signal has been used for other purposes such as reduction of power consumption in an operation mode generated in the DRAM or battery backup (BBU). That is, when the DRAM control signals satisfy a specific timing condition (the CBR mode is maintained over 100 xcexcs, namely a self-refresh /RAS pulse width (tRASS) is over 100 xcexcs), a refresh request signal is automatically generated by the refresh timer unit 31 without an external control signal, and thus RAS group control signals are automatically generated in the device, thereby performing the refresh operation according to the internally-generated address. This refresh operation is called a self-refresh operation.
The self-refresh mode is used to perform a low power operation or store data for an extended period of time. In the self-refresh mode, all of the input pins including the clock but excluding a clock enable pin cke are inactivated, not only the refresh address but also a refresh entry command are internally generated, and thus a generation period thereof is increased to reduce power consumption.
When the whole bank remains in an idle state, a chip selection signal /CS, a RAS bar signal /RAS, a CAS bar signal /CAS and a clock enable signal CKE reach a low level, and a write enable signal /WE reaches a high level, thereby entering the self-refresh mode. Once the self-refresh mode is started, all the input pins except for the clock enable pin cke are ignored.
In order to terminate the self-refresh mode, the clock buffer should be normalized by normally inputting a clock, and transforming the clock enable signal CKE to a high level. The SDRAM has an idle state after an active to active command delay time tRC. Here, it is possible to input a different command.
In general, the time interval for refreshing all the rows of the cell array, namely the time length between the refresh operation of the row of the memory cell array and the succeeding refresh operation thereof is called a refresh period. For example, in the case of the 16 megabit DRAM having a cell array constituted of 2048 rowsxc3x97512 columnsxc3x9716 bits and performing 2K(=2048) refresh cycles in a period, when a maximum time interval (namely, the refresh period) for refreshing 512 memory cells connected to one row is 128 ms, it is necessary to sequentially refresh 2048 rows in the time interval. Here, an inter-cycle time interval, namely a refresh clock period, is about 62.5 xcexcs (=128 ms÷2048 rows), and one refresh cycle (for example, 80 to 200 ns) is performed in every time interval, 62.5 xcexcs.
FIG. 2 is an explanatory diagram illustrating a self-refresh order in a conventional 128M DRAM. As shown in FIG. 2, 4096 word lines WL0-WL4095 exist in one bank 10 of the 128M DRAM. The time for self-refreshing all the word lines WL0-WL4095 is 64 ms, and thus one word line is refreshed every 15.6 xcexcs. Accordingly, a consumption current It is represented by the following formula:
It=4096xc3x97Iref+Istb
Here, It represents a consumption current for 64 ms, Iref represents a consumption current for refreshing one word line, and Istb represents a consumption current continuously consumed by the memory circuit in the self-refresh mode.
FIG. 3 is a graph plotting the consumption current against time in the self-refresh mode.
FIG. 4 is a circuit diagram illustrating a conventional circuit for generating an internal address. Here, 12 binary counters C1-C12 are used to refresh 4096 word lines WL0-WL4095.
The 4096 word lines should be refreshed once every 64 ms regardless of their order. Therefore, word lines 0 to 4096 are designated by using the binary counters C1-C12 having addresses 0 to 22.
FIG. 5 is a circuit diagram illustrating one of the binary counters C1-C12 composing the conventional circuit for generating the internal address. As depicted in FIG. 5, each binary counter includes: an inverter 41 for receiving a refresh signal REFD; a NAND gate 42 for receiving the output signal from the inverter 41 and an input signal RCAB; an inverter 43 for receiving the output signal from the NAND gate 42; an inverter 44 for receiving a signal of a node Nd1; a clock inverter 45 for receiving the output signal from the inverter 44, inverting the signal according to the output signal from the NAND gate 42 and the output signal from the inverter 43, and outputting the inverted signal to a node Nd2; an inverter 46 for receiving the signal of the node Nd2, and outputting the inverted signal to a node Nd3; a clock inverter 47 for receiving the signal of the node Nd3, inverting the signal according to the output signal from the NAND gate 42 and the output signal from the inverter 43, and outputting the inverted signal to the node Nd2; a clock inverter 48 for receiving the signal of the node Nd3, inverting the signal according to the output signal from the NAND gate 42 and the output signal from the inverter 43, and outputting the inverted signal to a node Nd4; an inverter 49 for receiving the signal of the node Nd4, and outputting the inverted signal to the node Nd1; a clock inverter 50 for receiving the signal of the node Nd1, inverting the signal according to the output signal from the NAND gate 42 and the output signal from the inverter 43, and outputting the inverted signal to the node Nd4; a NAND gate 51 for receiving the signal of the node Nd1 and the input signal RCAB; an inverter 52 for receiving the output signal from the NAND gate 51, and outputting the inverted signal RCAa; and an inverter 53 for receiving the signal of the node Nd3, and outputting the inverted signal RAaB.
When the refresh signal REFD has a high level, the binary counter circuit latches the signal of the node Nd3 with the clock inverter 47 and the inverter 46. The latched signal of the node Nd3 is inputted to the NAND gate 51 through the clock inverter 48 and the inverter 49. When the refresh signal REFD has a low level and the input signal RCAB has a high level, the signal of the node Nd1 is inverted through the inverter 44, the clock inverter 45 and the inverter 46, and the inverted signal is transmitted to the node Nd3. In addition, the signal of the node Nd1 is latched by the clock inverter 50 and the inverter 49. The signal of the node Nd3 which is the output signal from the inverter 46 is outputted as the output signal RAaB of the binary counter circuit through the inverter 53.
FIG. 6 is a waveform diagram illustrating outputs from the conventional circuit for generating the internal address.
As illustrated in FIG. 6, whenever the refresh signal REFD falls from a high to a low level, the binary counter circuit reduces one output signal RAaB, thereby sequentially selecting the 4096 word lines.
However, the low power DRAM does not refresh wholeword lines of the bank, but selectively refreshes partial word lines. Here, the conventional circuit for generating the internal address in the semiconductor memory device cannot sequentially generate only the addresses of the word lines in a predetermined region.
Accordingly, it is an object of the present invention to provide a circuit for generating an internal address which can reduce power consumption in a self-refresh operation, by generating an internal refresh address to refresh a partial array selected according to an external command.
In order to achieve the above-described object of the invention, there is provided a circuit for generating an internal address in a semiconductor memory device, including: a counter unit having a plurality of binary counters for generating internal address signals for wholly or partially refreshing word lines of a bank according to a setup value of a memory; and a control unit for receiving a most significant signal and a second most significant signal of the counter unit, a first select signal and a second select signal for deciding a word line region of the bank to be activated, and a self-refresh signal and a refresh signal, and generating a signal for controlling the operation of the counter unit, a most significant internal address signal, and a second most significant internal address signal, so that the output from the binary counters can be synchronized with the refresh signal and toggled, or fixed at a low level according to the received signals.
The counter unit includes: an M-th counter unit for receiving the refresh signal, the control signal from the control unit and a power voltage, and generating the sequentially-increased most significant internal address signal and a counter output signal; an M-1th counter unit for receiving the refresh signal, the control signal from the control unit, and the counter output signal from the 12th counter unit, and generating the second most significant internal address signal and a counter output signal; and first to M-2th counter units for respectively receiving the refresh signal and the counter output signal from preceding binary counter units, and generating the internal address signal and counter output signal.
The M-1th and M-th counter units are binary counters for sequentially increasing output signals.
The first to M-2th binary counter units are binary counters for sequentially decreasing output signals.
The period of the refresh signal is greater by a factor of 2N when the address output signals of the first to M-th counter units are fixed at a low level than when the address output signals of the first to M-th counter units are not fixed at a low level (N is the number of address output signals fixed at a low level).
The first select signal is a signal for selecting a self-refresh of a half region of the bank.
The second select signal is a signal for selecting a self-refresh of a quarter region of the bank.